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data sheet, v1.5, may 2005 never stop thinking. hye18p128160af-9.6 hye18p128160af-12.5 hye18p128160af-15 synchronous burst cellularram tm (1.5g) cellularram memory products
edition 2005-5 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2005. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hye18p128160af-9.6 hye18p128160af-12.5 hye18p128160af-15 synchronous burst cellularram tm (1.5g) cellularram data sheet, v1.5, may 2005 memory products
template: mp_a4_v2.0_2003-06-06.fm hye18p128160af-9.6, hye18p128160af-12.5, hye18p128160af-15 revision history: 2005-5 v1.5 previous version: 1.4 (target data sheet) page subjects (major chang es since last revision) 23 dpd duration time adjusted 30 , 31 row boundary crossing is not supported in all cases 19 , 37 , 41 cre timing clarified in asynchronous control register access previous version: 1.3 (target data sheet) all min. duration of dpd mode is set to 1ms 14 , 19 , 20 , 37 , 45 ub , lb low required for register read (fcr) 19 , 20 , 45 clarified wait behavior in synchronous register access 18 bcr.bit6 has no effect. 34 didr.bit15 reads out the information of pa ge size. if no use, please ignore the bit. 56 adjusted the values of operating currents previous version: 1.2 (target data sheet) page subjects (major chang es since last revision) all adjusted clk frequency target vs. latency code in fixed latency mode previous version: 1.1 (target data sheet) all v dd , min = 1.7v (contact factory for the part of 1.65v min) all wireless operating temperature goes down to - 30c all variable lat=2 reaches 66mhz max for 12.5 part 10, 11 j5 and j6 ball : ?nc? to ?rfu? 33, 56 density and design version fields are added to didr. asynchronous value change in t ohz , t wp, t ds. t ax removed from the spec. (per spec alignment) synchronous value change in t cwt , t css, t ckh/l, t sp, t t, t koh per spec alignment synchronous t kadv is added to specify timing requirement between last data-in to new burst_init. previous version: 1.0 (target data sheet) all all the spec features compatib le to hye18p64160ac v1.1 spec. we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
template: mp_a4_v2.0_2003-06-06.fm
hye18p128160af-9.6/12.5/15 128m synchronous burst cellularram tm (1.5g) data sheet 6 v1.5, 2005-5 1overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 hye18p128160af-9.6/12.5/15 ball configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 hye18p128160af-9.6/12.5/15 ball definition and description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.6 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.1 asynchronous commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6.2 synchronous commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.1 power-up and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 access to the control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 refresh control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.3.1 partial array self refresh (pasr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.3.2 deep power down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3.3 temperature compensated self refresh (tcsr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.3.4 power saving potential in standby when applying pasr, tcsr or dpd . . . . . . . . . . . . . . . . . . 24 2.3.5 page mode enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4 bus control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.4.1 latency mode / code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.1.1 variable latency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.4.1.2 fixed latency mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.1.3 burst write always produces fixed latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4.1.4 burst interrupt operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4.1.5 end-of-row condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 2.4.2 read burst configurations/sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.4.3 wait signal in synchronous burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.4.4 output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.5 self-refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.6 device id register (didr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.7 consideration on address skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.8 sram-type mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.1 asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.8.2 page mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.8.3 asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.9 nor-flash-type mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.9.1 synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.9.2 burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.9.3 synchronous control register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.9.4 asynchronous write with address latch (adv ) control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.10 synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.10.1 synchronous read mode including burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.10.2 synchronous write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.11 general ac input/output reference waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.2 recommended power & dc operation ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 3.3 output test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.4 pin capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 4 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 appendix : s/w register entry mode (?4-cycle method?) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
data sheet 7 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) figure 1 cellularram - interface configuration options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2 standard ballout - hye18p128160af-9.6/12.5/15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 functional block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 4 power up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 5 the two control registers (write and read access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6 control register write (scr) in asynchronous command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7 control register read (fcr) in asynchronous command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8 control register write (scr) in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 figure 9 control register read (fcr) in synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10 pasr programming scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 11 pasr configuration example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12 dpd entry and exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13 variable latency mode - functional diagram (lat=2, variable, wc=0 shown) . . . . . . . . . . . . . . . 28 figure 14 latency code - functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15 burst interrupt after burst_init command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 16 wait timing and recommended operation at the end of row . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 17 wait function by configuration (wc) - lat=2, wp=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figure 18 device id register (didr) mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19 timing diagram of address skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 20 asynchronous read - address controlled (cs = oe = v il , we = v ih , ub and/or lb = v il , cre = v il, adv = v il ) 36 figure 21 asynchronous read (we = v ih , cre = v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 22 asynchronous control register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 23 asynchronous page read mode (cre = v il, adv = v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 24 asynchronous write - we controlled (oe = v ih or v il , cre = v il ) . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 25 asynchronous write - cs controlled (oe = v ih or v il , cre = v il ). . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 26 asynchronous write - ub , lb controlled (oe = v ih or v il , cre = v il ) . . . . . . . . . . . . . . . . . . . . . 41 figure 27 asynchronous write to control register (oe = v ih or v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 28 synchronous read burst (cre = v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 29 burst suspend (cre = v il ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 30 synchronous control register read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 31 asynchronous write with address latch (adv ) control (followed by single-burst read) . . . . . . . . 47 figure 32 asynchronous write with address latch (adv ) control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 33 asynchronous write to control register in nor-flash mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 34 synchronous write burst (cre = v il ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 35 synchronous write command with extended t css . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 36 synchronous write to control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 37 synchronous write burst followed by synchronous read burst. . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 38 synchronous read burst followed by synchronous write burst. . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 39 dc / ac output test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 40 pg-vfbga-54 (plastic very thin fine pitch ba ll grid array package - green package) . . . . . . . 57 figure 41 s/w register entry timing (address input = 7fffffh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 42 rcr mapping in s/w register entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 43 bcr mapping in s/w register entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 44 didr mapping in s/w register read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
hye18p128160af-9.6/12.5/15 128m synchronous burst cellularram tm (1.5g) data sheet 8 v1.5, 2005-5 table 1 product selection & marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 2 ball description - hye18p128160af-9.6/12.5/15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 table 3 asynchronous command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 4 description of asynchronous commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5 synchronous command table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 6 description of synchronous commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 7 timing parameters for dpd operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8 standby currents wh en applying pasr, tcsr or dpd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 9 latency mode / code configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 10 burst sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 11 output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12 timing parameters - address skew . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 13 timing parameters - asynchronous read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 14 timing parameters - asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 table 15 timing parameters - synchronous read burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 16 timing parameters - asynchronous write with adv control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 17 timing parameters - synchronous read/write burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 18 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 19 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 20 dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 22 pin capacitances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 21 operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
data sheet 9 v1.5, 2005-5 128m synchronous bu rst cellularram tm (1.5g) cellularram hye18p128160af-9.6 hye18p128160af-12.5 hye18p128160af-15 1overview 1.1 features high density (1t1c-cell) synchr onous 128mbit pseudo-static ram designed for cell phone applications - low power, high density, refresh-free operation (cellularram) cellularram1.5g of more features, maintaining functional-compatibility to 1st-generation cellularram organization 8m 16 high bandwidth: ? 104 mhz synchronous burst read/write, 20 ns page read (16-word), 70 ns random access 1.8 v single power supply ( v dd for core and v ddq for i/o) low power optimized design ? i active = 25 ma @70 ns random cycle (with output disabled) ? i sb = 250 a, data retention mode ? i dpd = < 10 a (typ), non-data retention mode low power features ? partial array self-refresh (pasr) ? deep power down mode (dpd) ? temparature compensated self-refresh (tcsr) by the control of on-chip temperature sensor (octs) user configurable interface supporting three different access protocols (values from 9.6 part) ? asynchronous sram protocol, 70 ns random access cycle time, 20 ns page mode (read only) cycle time ? nor-flash burst protocol, 70 ns write cycle time, 104 mhz burst mode read cycle ? full synchronous interface prot ocol, 70 ns random cycle time, 104 mhz burst mode read/write cycle user settings for nor-flash burst or in synchronous mode ? fixed burst length of 4/8/16/32 words or continuous burst mode ? latency mode (variable or fixed) and various latency codes at desired clk frequency ? wrap mode function available for both read and write burst ? wait signal polarity and timing configurable ? driver strength of full, 1/2, or 1/4 write burst operates at fixed latency regardless of latency mode 2 sets of programmable registers (rcr & bcr) accessed (set or fetch) by cre-pin control or s/w entry mode 1 set of read-only register for device id accessed via fetch register command byte read/write control by ub /lb wireless operating temperature range from -30 c to +85 c pg-vfbga-54 chip-scale package - green product (9 6 ball grid) table 1 product selection & marking hye18p128160af -9.6 -12.5 -15 maximum input clk frequency (mhz) lat = 2 66 66 40 lat = 3 104 80 66 min. random cycle time ( t rc ) 70 ns 70 ns 85 ns ordering information contact factory contact factory hy e 18 p 128 16 0 a f infineon memory product wireless temperature range -30 c to +85 c 1.8v supply cellularram product family 128m x16 synch burst product version green package 64: 64m w: kgd (wafer form) 123 d b c e f g a0 a 6 45 dq8 lb a1 oe ub a2 cre a3 a4 cs dq0 dq9 dq10 a5 a6 dq1 dq2 dq3 a7 dq11 dq12 a16 a14 a15 v dd a12 dq15 dq4 a13 dq5 dq6 we dq7 v ddq h j a8 v ss a9 a10 clk adv a11 a20 nc nc a21 v ssq wait a17 dq14 dq13 a19 a18 nc (a22) top-side view (ball down) j4 is nc for 64mb and a22 for 128mb
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) overview data sheet 10 v1.5, 2005-5 1.2 general description the synchronous burst cellularram tm (1.5g) (cellularram) is designed to better serve the growing memory density and bandwidth demand in 2.5g and 3g cellular phone application. its high density 1t1c-cell concept, the multi-protocol interface capab ilities, its highly optimized low power design and its refr esh-free operation make the cellularram the perfect fit for advanced baseband applications. configured in synchronous burst mode, a peak bandwidth of > 200 mbyte/s is achieved at the max. clock rate of 104 mhz. the burst length can be programmed and set to either fixed burst lengths of 4, 8, 16- or 32-words 1) or set to continuous mode. the 16-word burst mode is spec ially designed for cached processor designs to speed up cache re-fill operations. the addition of fixed latency mode to 1st-generation cellula rram expands the support into legacy application where nor-type burst flash has been adopted. in nor-flash interface, burst read accesses are synchronous whereas write accesses are of asynchronous nature. this is to retain co mpatibility to today?s nor-flas h protocols and thus to make sure that existing baseband designs do get instantly a performance gain in read di rection by deploying the nor-flash burst protocol. the different access protocols that are suppor ted by the cellularram are illustrated in figure 1 . data byte control (ub , lb ) is featured in all modes and provides dedicated lower and upper byte access. figure 1 cellularram - interface configuration options the cellularram can be operated from a single 1.8 v power supply feeding the core and the output drivers. the chip is fabricated in infineon technologies advanced low power 0.11 m process technology and comes in a pg-vfbga-54 package. 1) 1 word is equal 16 bits 128mb cellularram (fbga-54) sram i/f read: async/ page sync. burst sync burst write: async async w/ adr latch sync burst 128mb cellularram (fbga-54) nor-flash i/f 128mb cellularram (fbga-54) sync. i/f clk adv wait 128mb cellularram (fbga-54) clk adv cre a22-a0 dq15-dq0 128mb cellularram (fbga-54) cre a22-a0 dq15-dq0 wait asynchronous i/f sync. burst i/f & nor-flash burst & asynchronous i/f pinning: protocols: clk=adv=low and wait ignored in asynchronous i/f cs we oe cs we oe clk adv wait cs we oe cs we oe ub lb cs we oe ub lb
data sheet 11 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) overview 1.3 hye18p128160af-9.6/12.5/ 15 ball configuration figure 2 standard ballout - hye18p128160af-9.6/12.5/15 note: figure 2 shows top view 123 d b c e f g a0 a 6 45 dq8 lb a1 oe ub a2 cre a3 a4 cs dq0 dq9 dq10 a5 a6 dq1 dq2 dq3 a7 dq11 dq12 a16 a14 a15 v dd a12 dq15 dq4 a13 dq5 dq6 we dq7 v ddq h j a8 v ss a9 a10 clk adv a11 a20 rfu rfu a21 v ssq wait a17 dq14 dq13 a19 a18 a22
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) overview data sheet 12 v1.5, 2005-5 1.4 hye18p128160af-9.6/12.5/15 ball definition and description table 2 ball description - hye18p128160af-9.6/12.5/15 ball type detailed function clk input clock signal in synchronous burst mode, address and command inputs and data are referenced to the positive (rising) edge of clk. in asynchronous sram-type mode and write accesses in nor-flash operation mode, the clk signal must be tied down to low. cre input control register enable cre set to high enables the access to the control register map. by applying the set control register (scr) command (see table 3 ) the address bus is loaded into the selected control register, while fetch control register (fcr) reads the contents of it onto dq pins. adv input address valid adv signals in nor-flash and full synchronous mode that a valid address is present on the address bus. in nor-flash read mode and full synchronous mode the address is latched on the programmed clock edge while adv is held low. in nor-flash write mode adv can be used to latch the address, but can be held low as well. in asynchronous sram-type mode adv needs to be active, it may be tied to low. cs input chip select cs enables the command decoder when low and disables it when high. when the command decoder is disabled new commands are ignored, addresses are don?t care and outputs are forced to high-z. internal operations, however, continue. for the details, please refer to the command tables in chapter 1.6 . oe input output enable oe controls dq output driver. oe low drives dq, oe high sets dq to high-z. we input write enable we set to low while cs is low initiates a write command. ub , lb input upper/lower byte enable ub enables the upper byte dq15-8 (resp. lb dq7 ? 0) during read/write operations. ub (lb ) deassertion prevents the upper (lower) byte from being driven during read or being written. wait output 3-state wait state signal in synchronous mode, wait signal indicate s the host system when the output data is valid during read and when the input data should be asserted during write operation, though monitoring of wait is not mandatory fo r write burst, since a write burst operates at fixed latency always. in asynchronous mode, the signal has to be ignored. a <22:0> input address inputs during a control register set operation by cre access, the address inputs define the register settings. dq <15:0> i/o data input/output the dq signals 0 to 15 form the 16-bit data bus. 1 v dd 1 v ss power supply power supply, core power and ground for the internal logic. 1 v ddq 1 v ssq power supply power supply, i/o buffer isolated power and ground for the output buffers to provide improved noise immunity. 2 rfu ? reserved for future use (rfu) please do not connect. j5 and j6 are reserved for future use. see ballout in figure 2 on page 11 .
data sheet 13 v1.5, 2005-5 128m synchronous bu rst cellularram tm (1.5g) cellularram hye18p128160af-9.6 hye18p128160af-12.5 hye18p128160af-15 1.5 functional block diagram figure 3 functional block diagram address decode async/ page i/f 1t1c-cell memory array (8m x16) mux control logic cs we oe ub lb clk adv cre a22-a0 dq7-dq0 sync. burst i/f wait additional pins necessary to operate the device in nor-flash and synchronous mode nor-flash burst i/f dq15-dq8
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) data sheet 14 v1.5, 2005-5 1.6 commands the supported command set depends on the selected operation mode. by default the cellularram device is reset to the asynchronous sram-type mode after power-up. to put the device in a different operation mode the bus configuration register (bcr) must be programmed first accordingly. the valid control input states and sequences are listed below in asynchronous commands (while clk is held low) or synchronous commands. other control signal combinations are not supported. 1.6.1 asynchronous commands in the sram-type operation mode, all commands are of asynchronous nature. write operation in nor-flash mode is done asynchronously as well. table 3 lists the asynchronous commands and clk has to be held low for entire asynchronous mode operation. note: ?l? represents a lo w voltage level, ?h? a high voltage level, ?x? re presents ?don?t care?, ?v? represents ?valid?. table 3 asynchronous command table 1) 1) clk has to be held low for entire asyn chronous operation. amax is a22 for 128mb. operation mode power mode cs adv we oe ub / lb cre a19 a18 amax - a0 dq15:0 read active l l h l l 2) 2) table 3 reflects the behaviour if ub and lb are asserted to low. if only either of the signals, ub or lb , is asserted to low only the corresponding data byte will be output or written (ub enables dq15 - dq8, lb enables dq7 - dq0). l v v adr dout write active lllx 3) 3) during a write access invoked by we set to low the oe signal is ignored. l 2) lvvadr din set control register (scr) active lllx 3) xhl h l l rcr din bcr din x fetch control register (fcr) active llhllhl h x l l h x rcr bits bcr bits device id no operation standby~active 4) 4) stand-by power mode applies only to the case when cs goes low from deselect while no address change occurs. toggling address results in active power mode. also, no operation from any active power mode by keeping cs low consumes the power higher than stand-by mode. lxhhxlxxx high-z deselect standby hxxxxxxxx high-z dpd 5) 5) after entry, cs has to be held high to maintain dpd. cs low-going starts wake-up out of dpd and automatically reset dpd control bit (rcr bit 4) to be diabled whether it is scr comman d or not. all the other contents of control registers should be maintained during dpd in the same state when it was before this mode. dpd hxxxxxxxx high-z table 4 description of asynchronous commands mode description read the read command is used to perform an asyn chronous read cycle. the signals, ub and lb , define whether only the lower, the upper or the whole 16-bit word is output. write the write command is used to perform an asynchronous write cycle. the data is latched on the rising edge of either cs , we , ub , lb , whichever comes first. the signals, ub and lb , define whether only the lower, the upper or the whole 16-bit word is latch ed into the cellularram.
data sheet 15 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) 1.6.2 synchronous commands in nor-flash-type mode read commands are performed in a synchronous burst, whereas both read and write in synchronous mode. all synchronous commands are defined by the states of the control signals cs , adv , and we (ub , lb and oe controls output at read asynchronously and ub , lb masks input data during write in synchronous way) at the positive (rising) edge of the clock signal, clk. to enable the synchronous commands, the device has to be programmed in the bus configuration register (bcr) first accordingly. table 5 lists the truth table for the supported synchronous commands. set control register the control registers are loaded via the address inputs a19, a15 - a0 performing an asynchronous write access. please refer to the control register description for details. the scr command can only be iss ued when the cellularram is in idle state. fetch control register the content of selected control register is loaded via dq15-dq0 by performing this command. please refer to the control register description for details. the fcr command can only be issued when the cellularram is in idle state. no operation the nop command is used to perform a no operation to the cellularram, which is selected (cs = 0). operations already in progress are not affected. power consumption of this command mode varies by address change and initiating condition. deselect the deselect function prevents ne w commands from being executed by the cellularram. the cellularram is effectiv ely deselected. i/o signals are put to high impedance state. dpd dpd stops all refresh-related activiti es and entire on-chip circuit operation. current consumption drops below 25 a. wake-up from dpd also requires 150 s to get ready for normal operation. the use of dpd mode for duration of no longer than 1ms is not allowed. table 5 synchronous command table 1) 1) synchronous commands are sampled at rising edge of clk except dpd. amax is a22 for 128mb. operation mode power mode clk cs adv we ub / lb cre a19 a18 amax - a0 dq15:0 burst init read active l->h l l h l l v v adr x burst read active l->h l h x l 2) x x x x dout 3) burst init write active l->hll lxl vvadr x burst write active l->h l h x l 2) xxxx din set control register active l->hll lxhl h l l rcr din bcr din x fetch control register active l->h l l h l h l h x l l h x rcr bits bcr bits device id no operation standby~active 4) l->h l h h x l x x x high-z 5) deselect standby l->h h x x x x x x x high-z dpd 6) dpd l h x x x x x x x high-z table 4 description of asynchronous commands (cont?d) mode description
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) data sheet 16 v1.5, 2005-5 note: ?l? represents a lo w voltage level, ?h? a high voltage level, ?x? re presents ?don?t care?, ?v? represents ?valid?. 2) table 5 reflects the behaviour if ub and lb are asserted to low. if only either of the signals, ub or lb , is asserted to low only the corresponding data byte will be output or written (ub enables dq15 - dq8, lb enables dq7 - dq0). if both signals are disabled the device is put in deselect mode. 3) output driver controlled by the asynchronous oe control signal 4) stand-by power mode applies only to the case when cs goes low from deselect while no address change occurs. no operation from any active power mode by keeping cs low consumes the power higher than stand-by mode. 5) the asynchronous oe control signal has to be asserted to ?h?. 6) after entry, cs has to be held high to maintain dpd. cs low-going starts wake-up out of dpd and automatically reset dpd control bit (rcr bit 4) to be diabled whether it is scr command or not. all the other content s of control registers should be maintained during dpd in the same state when it was before this mode. table 6 description of synchronous commands mode description burst init the burst init command is used to in itiate a synchronous burst access and to latch the burst start address. the burst length is determined by the setting in the bus configuration register. burst read the burst read command is used to perform a synchronous burst read access. the first data is output after the number of clock cycles as defined by the programmed latency mode. burst write the burst write command is used to perform a synchronous burst write access. the point of time when the first data is written is indicated by the wait signal. it varies with the selected clock frequency and the occurrence of a refresh cycle. set control register the control registers are loaded via the address inputs a19, a15 - a0 performing a single word burst. please refer to the control register description for details. the scr command can only be issued when th e cellularram is in idle state and no bursts are in progress. fetch control register the content of selected control register is loaded on dq15 - dq0 by performing this command like a single read burst. please refer to the control register description for details. the fcr command can only be issued when the cellularram is in idle state an d no bursts are in progress. no operation the nop command is used to perform a no operation to the cellularram, which is selected (cs = 0). operations already in progress are not affected. deselect the deselect function prevents new commands from being executed by the cellularram. the cellularram is effectively deselected. i/o signals are put to high impedance state. dpd dpd stops all refresh-related activiti es and entire on-chip circuit operation. current consumption drops below 25 a. wake-up from dpd also requires 150 s to get ready for normal operation. the use of dpd mode for duration of no longer than 1ms is not allowed.
data sheet 17 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2 functional description 2.1 power-up and initialization the power-up and initialization sequence guarantees that the device is preconditioned to the user?s specific needs. like conventional drams, the cellularram must be powered up and initialized in a predefined manner. v dd and v ddq must be applied at the same time to the specified voltage while the input signals are held in ?deselect? state (cs = high). after power on, an initial pause of 150 s is required prior to the control register access or normal operation. failure to follow these steps may lead to unpredictable start-up modes. please note the default operation mode after power up is the asynchronous sram i/f mode (see chapter 2.4 ). figure 4 power up sequence vdd, vddq t pu =150 s ready for normal operation vdd,vddq,min
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 18 v1.5, 2005-5 2.2 access to the contro l register map [disclaimer] amax for 64mbit cellularram is a21. a22 for 128mbit density. write access to the control register map is enabled by applying the scr command asserting the cre-pin to high. in combination with cre set to high, pin a19 designates the operation to one of either control registers. pin a19 set to low selects the refresh control register (rcr), pin a19 set to high addresses the bus configuration register (bcr), while a18 is applied low. write and read access to the control registers is also available at s/w entry method. for details, please refer to ?appendix : s/w register entry mode (?4-cycle method?)? on page 58 . figure 5 the two control registers (write and read access) a22 is not shown in figure 5 . it has to be set to ?0?. figure 6 control register write (scr) in asynchronous command burst length a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 bw wp wc imp om latency mode/code a19 1 a16 0 a17 0 a18 0 a20 0 pasr a0 a1 a2 a3 a4 a5 a6 a7 a8 a18 a20 tcsr pm 0 0 0 dpd a19 0 0 0 0 0 0 0 0 0 0 a9 a10 a11 a12 a13 a14 a15 a16 a17 a19 is the selection address between bcr and rcr bus control register (bcr) refresh control register (rcr) all '0' are reserved bits and must be set to zero. a21 0 a21 0 0 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 by scr by fcr by scr by fcr 0 0 0 setting of bit.a6 has no effect don't care a22-a0 op code cs we ub, lb dqx cre a19 initiate control register access latch opcode on address address bcr adv (latch opcode) write opcode 0(rcr), 1(bcr) (note 1) /cs has to start from high and end to high for completion of register access (note 1) (note 1) (notes) a22 is for 128m onl y.
data sheet 19 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description figure 6 shows scr command in asynchronous way. cre is asserted high and the op-code is loaded to the selected register via address bus. a19 selects either bcr (=1) or rcr (=0) while a18 is supplied low. adv may be held low for entire operation, but cs has to start from high, goes low, then back to high to complete the cycle. figure 7 control register read (fcr) in asynchronous command fcr command is introduced to this cellularram design so that the programmed content of the selected register can be checked. the timing diagram in figure 7 is identical to asynchronous read operation except cre state. figure 8 control register write (scr) in synchronous mode don't care amax-a0 cs we ub, lb dq15-dq0 t rc a19, a18 cre adv oe opcode select register 00 b (rcr), 10 b (bcr), x1 b (didr) (note 1) /cs has to start from high and end to high for completion of register acc e (note 1) (note 1) don't care cs oe ub, lb we dq15-dq0 a22-a0 op code clk wait adv cre a19 initiate control register access latch control register address latch control register value 0(rcr),1(bcr) > twc,min (notes) 1. a22 is for 128m only. 2. wp=0 is shown. (no effect by wc, lm, or lc program )
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 20 v1.5, 2005-5 scr can be performed in synchronous way. cre sampled hi gh at rising edge of clk initiates and completes the operation. please note than wait goes deasserted after synchronous scr command is decoded and cs has to go high to complete the cycle before issuing new command. figure 9 control register read (fcr) in synchronous mode fcr in synchronous command is identical to a read burs t of single-bit, but high cre enables read access from the register, not from the memory array. please note than wait goes deasserted after synchronous scr command is decoded and oe becomes low. don't care cs oe we dq15-dq0 amax-a0 clk adv t cl k cre a19, a18 s el ect regi ster 00 b (rcr), 10 b (bcr), x1 b (didr) opcode wait ub, lb (notes) wp=0 is shown. (no effect by wc, lm, or lc program)
data sheet 21 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2.3 refresh control register the refresh control register (rcr) allo ws to save stand-by power additionally by making use of the partial-array self refresh (pasr) and deep power down (dpd) features. the refresh control register is programmed via the control register set command (with cre = 1 and a19 = 0) and retains the stored information until it is reprogrammed or the device loses power. the field for the temperature-compensated self refresh (tcsr) is not in use since octs controls and adjusts refresh rate accord ing to die temperature. any setting of this field has no effect. please note that the rcr contents can only be set or changed when the cellularram is in idle state. rcr refresh control register (cre, a19 = 10 b ) amax-a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 rs 0 pm (tcsr) dpd 0 pasr field bits type 1) description rs 19 - register select 0 set to 0 to select this rcr (= 1 to select bcr). pm 7 wr page mode enable/disable in asynchronous operation mode the user has the option to toggle a0 - a3 in a random way at higher rate (20 ns vs. 70 ns) to lower access times of subsequent reads with 16-word boundary. in synchronous mode this option has no effect. the max. page length is 16 words. please note that as soon as page mode is enabled the cs low time restriction applies. this means that the cs signal must not be kept low longer than t csl = 4 s. please refer to figure 23 . 0 page mode disabled (default) 1 page mode enabled (tcsr) [6:5] na temperature compensated self refresh (not in use) the 2-bit wide tcsr field is not in use. on-chip temperature sensor (octs) adjusts the refresh period according to the actual temperature of die. since dram technology requires higher refresh rates at higher temperature this enables the device to lower power consumption in case of low or medium temperatures. all are reserved. setting has no effect. dpd 4 wr deep power down enable/disable the dpd control bit puts the cellularram device in an extreme low power mode cutting current consumption to less than 25 a. stored memory data is not retained in this mode. the settings of both control registers rcr and bcr are maintained during dpd. please note that the use of dpd mode for duration of no longer than 1ms is strictly prohibited. 0 dpd enabled 1 dpd disabled (default)
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 22 v1.5, 2005-5 2.3.1 partial array self refresh (pasr) by applying pasr the user ca n dynamically customize the memory capa city to one?s actual needs in normal operation mode and standby mode. with the activation of pasr there is no longer a power penalty paid for the larger cellularram memory capacity in case only e.g. 16 mbits are used by the host system. bit2 down to bit0 specify the active memory array and its location (starting from bottom or top memory location). the memory array outside the selected range is powered down immediately after the mode register has been programmed. advice for the proper register setting including the address ranges is given in figure 10 . figure 10 pasr programming scheme pasr is effective in normal operation and standby mode as soon as it has been configured by register programming. default setting is the entire memory array. figure 11 shows an exemplary pasr configuration where it is assumed that the application uses max. 32 mbit out of 128 mbit. pasr [2:0] wr partial array self refresh the 3-bit pasr field is used to specify the active memory array. the active memory array will be kept periodically refreshed whereas the disa bled parts will be excluded from refresh and previously stored data will get lost. th e normal operation still can be executed in disabled array, but stored data is not guaranteed. this way the customer can dynamically adapt the memory capaci ty to one?s need without paying a power penalty. please refer to figure 10 . 000 entire memory array (default) 001 lower 1/2 of the memory array (64 mb) 010 lower 1/4 of the memory array (32 mb) 011 lower 1/8 of the memory array (16 mb) 100 zero 101 upper 1/2 of the memory array (64 mb) 110 upper 1/4 of the memory array (32 mb) 111 upper 1/8 of the memory array (16 mb) res max-20, [18:8], 3 w reserved must be set to ?0? 1) wr: write-read access field bits type 1) description 0fffffh 1fffffh 3fffffh 000 001 010 011 3fffffh 300000h 200000h 000000h 100 101 110 111 pasr.bit2,1,0 pasr.bit2,1,0 8m 16m 32m 64m 8m 16m 32m 0m 64mb cellularram 8m 000000h 1fffffh 3fffffh 7fffffh 000 001 010 011 7fffffh 600000h 400000h 000000h 100 101 110 111 pasr.bit2,1,0 pasr.bit2,1,0 16m 32m 64m 128m 16m 32m 64m 0m 128mb cellularram 32m 32m 16m 8m 16m 16m 8m 8m 07ffffh 380000h 16m 16m 16m 0fffffh 700000h
data sheet 23 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description figure 11 pasr configuration example 2.3.2 deep power down mode to put the device in deep power down mode, the dpd control bit must be asserted to low and cs has to be pulled up and maintained high. once set into this extreme low power mode current consumption is cut down to less than 25 a until cs goes low automatically resetting th e dpd control bit to be disabled. all internal voltage generators inside the cellularram are s witched off and the internal self-refresh is stopped. this means that all stored memory information will be lost by entering dpd. only the register va lues of bcr and rcr are kept valid during dpd. a guard time of at least 150 s has to be met where no commands beside a nop must be applied to re-enter again standby or idle mode. figure 12 helps to overview how dpd mode is entered, maintained, then exited. dpd mode starts from the time when cs is high and the dpd control bits is programmed to low (enabled). then dpd ex it is simply initiated by seeing cs low resulting in automatic reset of the dpd control bit. the time wh en dpd mode is maintained should exceed 150 s for proper operation of the cellularram. figure 12 dpd entry and exit table 7 compares several methods available to suppress the power consumption down to deep level. since wake- up time is required for dpd, it is re commended to use pasr of zero range for relatively short duration in the mode. to chop completely off the residual power consumption, disconneting the power supply from the device must be better. table 7 timing parameters for dpd operation parameter symbol 9.6, 12.5, 15 unit note min. max. duration of dpd operation t dpd 150 ? s? dpd exit time t dpdx 10 ? s? dpd recovery time t r 150 ? s? 96mb deactivated 000000h 0fffffh rcr.bit 2,1,0= 010 active memory array defined by pasr to 32mb 32m activated 128mb cellularram don't care cs cre t r e x itin g d p d device in dpd (m aintaining) entering dpd step 1 (scr) rcr.bit4 =1 and /cs goes high step 2 (dpd) device is in dpd while /cs is held high we t wc t dpdx > 10us step 3 (dpd exit and normal operation) any /cs low (including scr command) starts the device exit fro m d p d . tr o f 1 5 0 u s is n e e d e d fo r w a ke -u p till first n o rm a l operation. the content of registers are maintained except dpd bit going back to disabled. t dpd > 150us
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 24 v1.5, 2005-5 2.3.3 temperature compensat ed self refresh (tcsr) the setting of this register has no effect any longer d ue to the use of octs. actual die temperature is measured and refresh rate is adjusted accordingly by octs. 2.3.4 power saving potential in standby when applying pasr , tcsr or dpd table 8 demonstrates the currents in st andby mode when pasr, tcsr or dpd is applied. tcsr is for reference only, since it reflects the reading of octs in stead of external programming of the register. the values in table 8 is not tested for all samples in every cases. for reference use only. 2.3.5 page mode enable/disable in asynchronous operation mode, the user has the option to enable page mode to toggle a0 - a3 in random way at higher cycle rate (20 ns vs. 70 ns) to lower access times of subsequent reads within 16-word boundary. write operation is not supported in the manner of page mode access. in synchronous mode, this option has no effect. the max. page length is 16 words, so which a0 - a3 is regarded as page-mode address. if the access needs to cross the boundary of 16-word (any difference in a22 - a4), then it should start over new random access cycle by toggling cs . please note that as soon as page mode is enabled the cs low time restriction app lies. this means that c s signal must not be kept low longer than t csl = 4 s. please refer to figure 23 . table 8 standby currents when applying pasr, tcsr or dpd operation mode power mode pasr rcr control wake-up phase active array standby [ a] no operation/ deselect standby tcsr no (octs) ? ? 85 70 45 15 pasr bit2-0 ? full 1/2 1/4 1/8 0 250 170 130 115 100 180 140 120 110 100 140 120 110 105 100 130 120 110 100 100 dpd deep power down dpd bit4 ~150 s0 25.0 10.0 pasr refreshed memory area a2 a1 a0 partial array self refresh 001 010 a0 entire memory array (def.) 000 a1 a2 a3 a4 a5 a6 a7 a8 a18 a20 (tcsr)* pm 0 0 0 max. case temp. a5 temperature-compensated self-refresh (no effect) 1 +85c (def.) +70c +45c +15c 0 1 0 a6 1 0 0 1 control reg control register select rcr bcr 0 1 a19 address bus control register power down deep power down mode enabled disabled (def.) 0 1 a4 011 lower 1/2 of memory array lower 1/4 of memory array lower 1/8 of memory array 101 110 111 upper 1/2 of memory array upper 1/4 of memory array upper 1/8 of memory array dpd zero 100 page mode page mode bit disabled (def.) enabled 0 1 a7 a19 0 a22, a21, a20, a18....a8: reserved, must be set to '0'. a21 0 the reading from octs will override this register setting. a22 0 0 refresh control register (rcr) (notes) a22 is for 128m only
data sheet 25 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2.4 bus control register the bus control register (bcr) specifies the interface configurations. for the various configuration options please refer to the register description below. the bus control register is programmed via the control register set command (with cre = 1 and a19 = 1) and retains the stored information until it is reprogrammed or the device loses power. most of bcr fields are assigned to configur e the cellularram in a proper way to operate in burst mode and there are some additions to 1st-generation cellularram such as fixed latency mode, 32-word burst, etc. please note that the bcr contents can only be set or changed when the cellularram is in idle state. note: bit 9 and bit 7 must be set to ?0? for proper operation and setting of bit 6 has no effect. bcr bus control register (cre, a19 = 11 b ) amax-a20 a19 a18-a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 0 om latency mode/code wp 0 wc 0 x imp bw burst length field bits type 1) description rs 19 - register select 1 set to 1 to select this bcr (= 0 to select rcr). op- mode (om) 15 wr operation mode the cellularram supports three different interface access protocols, the sram-type protocol with asynchronous read and write accesses the nor-flash-type protocol with synchronous read and asynchronous write accesses the full synchronous mode with synchr onous read and synchronous write accesses operating the device in synchronous mode maximizes bandwidth. the nor-flash type mode is the recommended mode for legacy baseband systems which are not able to run the synchronous write protocol. the opmode bit defines whether the device is operating in synchronous (fully or partially) mode or asynchronous mode. 0 nor-flash-type mode read: synchronous burst mode write: asynchronous access mode 0 full synchronous mode read: synchronous burst mode write: synchronous burst mode the mode of write operat ion, nor-flash or full synchronous, is adaptively detected, which means asynchronous write operation in nor-flash mode can be performed while clk is stopped at low. if a rising clock edge occurs within adv valid, full synchronous write is de tected. please refer to figure 31 on page 47 for asynchronous write and to figure 34 on page 50 for synchronous write. 1 sram-type mode (default) read: asynchronous access mode write: asynchronous access mode
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 26 v1.5, 2005-5 lm, lc [14], [13:11] wr latency mode / code the latency is the number of clk cycles from the burst_init command (the address valid strobe signal, adv sampled at positive edge of clk) to either the clk being able to sample 1 st valid data output (read burst) or to write 1 st valid data input to the memory (write). 1 st -generation cellularram only offers ?variable latency mode? which may assert more wait cycles than programmed in the register (lc: latency code) when the burst operaiton collides with on-going re fresh. due to variable number of wait states possible at this mode, the monitori ng wait signal is mandatory to use. the cellularram now adds the support on ?fixed latency mode? for the legacy system which does not monitor wait signal. the ch oice of the mode is done by bit. 14. the latency code defines the number of the latency and configured in bit. 13-11. bit.14=0 (default, variable latency mode), bit13-11 is; 010 variable latency 2, max 66mhz clk 011 variable latency 3 (default), max 104mhz clk bit.14=1 (fixed latency mode), bit13-11 is; 010 fixed latency 2, max 33mhz clk 011 fixed latency 3, max 52mhz clk 100 fixed latency 4, max 66mhz clk 101 fixed latency 5, max 75mhz clk 110 fixed latency 6, max 104mhz clk note: all others reserved. wp 10 wr wait polarity the wait polarity control bit allows the user to define the polarity of the wait output signal. the wait output line is used during a synchronous read burst to signal when the output data is invalid (wait is active). 0 active low 1 active high (default) wc 8 wr wait configuration the wait signal configuration control bit specifies whether the wait signal is asserted at the same time of the delay or whether it is asserted one clock cycle in advance to the data output or input. 0 wait is asserted during the delay 1 wait is asserted one data cycle before the delay (default) imp [5:4] wr output impedance for adaptation to different system characteristics the output impedance can be configured. 00 full drive strength of 25~30 ? impedance 01 half drive strength of 50 ? impedance (default) 10 quarter drive strength of 100 ? impedance bw 3 wr burst wrap the burst wrap control bit defines whether there is a wrap around within a burst access or not. in case of fixed 8-word burst length, this means that after word7 , word0 is going to be output in wrap mode. in case of continuous burst mode the internal addre ss counter will wrap from the last address, 7fffff h to 000000 h regardless of the setting. please note this setting is applied to both read and write burst. 0wrap 1 no wrap (default) field bits type 1) description
data sheet 27 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2.4.1 latency mode / code the latency code defines the number of clock cycles which pass before the first output data is valid within a read burst access (counting from the clock edge where adv was detected low) or the first data input becomes valid within a write burst access. the invalid state on dq pins is indicated by asserting wait signal active, so that the latency equals to the number of wait states. 2.4.1.1 variable latency mode 2 latency modes are supported in this design - variable or fixed. in variable latency mode, compatible to first- generation cellularram, the latency code programmed in bcr represents only the minimum latency of the cellularram, since the latency may be extended (means more wait states) if the burst collides with on-going self refresh operation. the wrap-off burst or continuous bu rst may continue across the row boundary (each row has bl [2:0] wr burst length via the burst length field the user can select between fixed burst lengths of 4, 8, 16, 32, or any arbitrary burst length until it reaches the end of row by choosing the continuous mode option. in continuous mode the burst length is controlled by the active low period of the control lines cs . please note this setting is applied to both read and write burst. 001 4-word burst 010 8-word burst 011 16-word burst 100 32-word burst 111 continuous (default) note: all others reserved. res 21, 20, [18:16], 14, 9, 7, 6, 4 - reserved must be set to ?0? except bit.6 which has no effect by setting. 1) wr: write-read access field bits type 1) description burst length burst length a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a15 bw wp wc imp om control reg control register select selects rcr selects bcr 0 1 a19 drive strength output impedance full drive 1/4 drive 0 0 a4 latency code latency latency code reserved code3 (def) 011 polarity wait polarity active low active high (def) 0 1 a10 opmode operation mode sync mode 0 1 a15 address bus control register timing wait configuration at delay one data cycle in advance (def) 0 1 a8 async./ page mode (def) a11 a12 a13 a19 1 code2 010 (note) all address fields not shown must be set to ?0? setting of bit.6 has no effect 0 0 1 a5 1/2 drive (def) 1 0 reserved 1 1 101 code4 100 code5 reserved code6 110 a2 a1 a0 all others reserved continuous (def) 111 8 010 4 001 16 011 wrap mode burst wrap wrap no wrap (def) 0 1 a3 length 0 lm latency mode all others 1 1 1 0 0 all others 0 1 variable fixed a14 0 32 100 1 0 1 1 code3 1 0 1 0 code2 a18 0 a14 bus control register (bcr)
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 28 v1.5, 2005-5 256-word size, coupled to every address of ff h ). since boundary crossing is not supported in cellularram 1.5g, the controller has to manage such a case by either terminating the ongoing burst at the end of row or issuing new burst command to continue with designated address location. refer to ?end-of-row condition? on page 30 for more details. the programmed latency code is only based on the case of new burst_init command from all precharged memory (usually cs toggling from high to low) when no refresh operat ion is performed. variable latency mode is capable of offering higher clk frequency at the given latency code. for example, latency code of 3 in variable latency can operate the cellularram at max 104mhz clk, but the same code in fixed latency only upto 52mhz. this unpredictable nature of latency code makes the moni toring of wait signal mandatory, since only wait signal can inform when the valid data is present. figure 13 variable latency mode - functional diagram (lat=2, variable, wc=0 shown) 2.4.1.2 fixed latency mode in the contrast to variable latency mode, the fixed latency mode guarantees that the initial latency of any burst operation always equals to the code programmed in bcr whether on-going refresh is in place or not. the latency code is derived from the longest path of the delay whic h includes refresh operation and initial burst access. therefore, the fixed latency limits clk frequency lower th an the same latency of variable latency mode (52mhz vs. 104mhz at latency code = 3). the row boundary crossing is not permitted . the number of inserted wait cycles, which is the latency code, increases along with the input clock frequency. please refer to table 9 for the proper setting. table 9 latency mode / code configuration latency mode latency code max. input clock frequency [mhz] -9.6 -12.5 -15 variable (bit.14=0) (default) 2666640 3 104 80 66 all others reserved reserved reserved don't care ce oe ub, lb we dq15-dq0 amax-a0 q0 adr clk wait adv q1 latency code2 (3 clocks) read command read command without refresh (lat=2) 3 clocks to first data q0 adr q1 latency code2 (5 clocks) read command read command with refresh (lat=2) 5 clocks to first data q2 (notes) wp=0, wc=0 is shown
data sheet 29 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description figure 14 latency code - functional diagram 2.4.1.3 burst write always produces fixed latency the monitoring of wait for a write burst may become blocking point to the system upgrading clk frequency. unlike wait is used to indicate valid data output on dq pins from the cellularram can be sampled at the controller during a read burst, the controller has to drive next data input onto dq pins in time once wait is de- asserted. to address this concern, the cellularram in this design offers fixed latency always for a write burst though latency mode bit is configured in variable latency (bcr.bit14=0). the fixed latency behavior of a write burst while read burst in variable latency mode applie s to burst_init situation. the controller has to observe maximum t csl (= 4 s) in case a write burst continues over long bursts. as discussed in ?burst interrupt operation? on page 30 , burst interrupt operation while cs being held low is another case which can not schedule refresh operation properly, so that t csl (= 4 s) limitation also applies. on the other hand, if bcr.bit14 is set to ?1?, the cellularram operates in fixed latency mode. the latency for a write burst, of course, is fixed at burst_init command. burst interrupt operation while cs being held low is the case which can not schedule refresh operation properly, so that t csl (= 4 s) limitation applies. fixed (bit.14=1) 2333320 3525233 4666640 5757552 6 104 80 66 all others reserved reserved reserved table 9 latency mode / code configuration (cont?d) latency mode latency code max. input clock frequency [mhz] -9.6 -12.5 -15 don't care control read n clk nop nop nop nop nop nop nop dqx q n+1 q n+2 q n+3 q n+4 q n+5 q n+6 q n+7 code2 code3 dqx q n+1 q n+2 q n+3 q n+4 q n+5 q n+6 q n+7 code4 q n+1 q n+2 q n+3 q n+4 q n+5 q n+6 dqx code5 q n+1 q n+2 q n+3 q n+4 q n+5 dqx code6 q n+1 q n+2 q n+3 q n+4 dqx
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 30 v1.5, 2005-5 2.4.1.4 burst interrupt operation when any burst is complete or needs to be terminated to start new burst, bringing cs high and back low in next clock cycle is usual and recommended. burst interrupt is referred to the case when the on-going burst is terminated by newly issued burst_init command without toggling cs. in case of doing this, special care has to be taken to avoid any malf unction of cellularram. in any case, the burst interrupt is prohibited until burst_ init command completes the first valid data cycle (first data output or first data input cycle) as shown in figure 15 . at new burst_init command, dq pins go into high-z if on- going burst is a read. in case of write burst being interrupted, the data input is masked, not updated to the memory location. figure 15 burst interrupt after burst_init command (1) in variable latency mode; read burst works at variable latency, but write burst has to meet fixed latency requirement. unlike normal burst_init situation from precharged memory, burst interr upt by a write burst does not schedule refresh operation. on-going read or write burst can be interrupted by a read burst. refresh is taken in place if needed, but additional wait cycles are added to the latency for a read burst. on-going read or write burst can be interrupted by a writ e burst. refresh is never scheduled in this case. cs low time being engaged with the interrupt by write burst should not exceed maximum t csl (= 4 s). (2) in fixed latency mode; the fixed latency mode is designed to completely guarantee the refresh operation at burst_init situation from the precharged memory (from cs high). however, any burst interrupt while cs is held low can not guarantee proper refresh operation in fixed latency mode. maximum t csl (= 4 s) limit should be observed for any burst operation whether it is interrupted or not. 2.4.1.5 end-of-row condition the cellularram in this design has the row size of 256-word, so that boundary between adjacent rows (= end of row) takes place at every address of ff h (ff h , 1ff h , 2ff h , ..). if the burst operation continues over the boundary when it is in continous burst mode or wrap-off burst advances, the controller should take care of it when the ongoing burst reaches the end of row. it may do terminate ongoing burst or issue new burst_init command of next row or random location different from next address. wait pin indicates when the ongoing burst meets the end of row condition. note: if the controller can do nothing with the ongoing burst at the end of row, the row boundary crossing operation will occur so that wait goes de-assert ed back with valid next data after a few clock cycles. monitoring wait don't care control burst n clk burst m code3 dqx dq n dq n+1 first clk cycle of burst interrupt allowed read goes into high-z w rite data is masked no interrupt or terminate wait (w c=1) (w c=0) (n ote) 1. w p =0 (active low ) is show n 2. read data at the burst interrupt cycle (?dq n+1 ?) is invalid data though w ait is not indicated yet
data sheet 31 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description is mandatory in this case, since the cellularram from different vendors may have not identical behavior as to row boundary crossing. please contact factory for advice. the end of row condition can be detected by tracking the address of ongoing burst, of course. since the row size may be different over the vendors, it is available to re ad out the row size through accessing device id register (didr). please refer to ?device id register (didr)? on page 34 for details. figure 16 depicts wait timing and recommended operation when the burst advances to the end of row. figure 16 wait timing and recommended operation at the end of row cs clk dqx no later than 3 rd clock after last data dq last-1 dq last last data wait (wc=1) (wc=0) [termination] dq last-1 dq last last data (wc=1) (wc=0) [interrupt] low high 2 clock cycles allowed for new burst_init adv (notes) wp=0 is shown
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 32 v1.5, 2005-5 2.4.2 read burst co nfigurations/sequences the numbers of words that are accessed during a burst is defined by the burst length field which is programmed in the bus control register. the user can either program fixed burst lengths of 4-, 8-, 16-, or 32-words or operate the device in continuous mode operation. the burst start address is latched by adv set to low at burst_init command time. an internal address counter then increments automatically the address with respect to the programmed burst length. continuous burst operation offers arbitrary length of burst until it reaches the end of row. in other words, unlike with fixed burst lengths, a continuous burst goes on until it is actively te rminated by bringing cs to high. the wrap mode option specifies whether the burst address overflows and restarts at address 0 (a4 - a0) or keeps incrementing. for the several possible burst sequences please refer to table 10 . table 10 burst sequences burst length starting address (a4 a3 a2 a1 a0) sequential burst addressing scheme (decimal) wrap on wrap off 1) 4 xxx00 xxx01 xxx10 xxx11 0 1 2 3 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 1 2 3 4 2 3 4 5 3 4 5 6 8 xx000 xx001 xx010 ? ? xx101 xx110 xx111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 ? ? 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 ? ? 5 6 7 8 9 10 11 12 6 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 16 x0000 x0001 x0010 ? ? x1101 x1110 x1111 0 1 2 ? 13 14 15 1 2 3 ? 14 15 0 2 3 4 ? 15 0 1 ? ? 13 14 15 ? 10 11 12 14 15 0 ? 11 12 13 15 0 1 ? 12 13 14 0 1 2 ? 13 14 15 1 2 3 ? 14 15 16 2 3 4 ? 15 16 17 ? ? 13 14 15 ? 26 27 28 14 15 16 ? 27 28 29 15 16 17 ? 28 29 30 32 00000 00001 00010 ? ? 11101 11110 11111 0 1 2 ? 29 30 31 1 2 3 ? 30 31 0 2 3 4 ? 31 0 1 ? ? 29 30 31 ? 26 27 28 30 31 0 ? 27 28 29 31 0 1 ? 29 30 31 0 1 2 ? 29 30 31 1 2 3 ? 30 31 32 2 3 4 ? 31 32 33 ? ? 29 30 31? 58 59 60 30 31 32? 59 60 61 31 32 33? 60 61 62 continuous 1) 1) wrap-off burst goes up to the end of row. n cn, cn+1, cn+2, ? cmax 2) (default, write burst) 2) cmax = end of row
data sheet 33 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2.4.3 wait signal in synchronous burst mode the wait signal is used in synchronous burst read mode to indicate to the host system when the output data is invalid. periods of invalid output data within a burst access might be caused either by first access delays, or by self-refresh cycles. to match with the flash interfaces of different microproce ssor types the polarity and the timing of the wait signal can be configured. the polarity can be programmed to either active low or active high logic. the timing of the wait signal can be adjusted as well. depend ing on the bcr setting the wait signal will be either asserted at the same time the data becomes invalid or it will be set active al ready one clock pe riod in advance. in asynchronous read mode including page mode, the wait signal is not used but always stays asserted as bcr. bit 10 is specified. in this case, sys tem should ignore wait state, since it does not reflect any valid information of data output status. figure 17 wait function by configuration (wc) - lat=2, wp=0 2.4.4 output impedance according to the setting of bcr.bit 4 and bit5, the output drive strength can be adjusted to full, one-half, or one- quarter strength. the choice must depend on loading condition of dq bus and speed requirement of the system. reduced-drive strength on very heavily loaded bus will slow down the sp eed too much, while fu ll drive strength on the bus of relatively light lo ading will result in unacceptab le noise. please refer to table 11 for general guidance of proper selection of output drive strength. table 11 output impedance 2.5 self-refresh the cellularram relieves the host system from triggering and commanding re fresh-operations like it is the case with conventional drams by performing automatic self-refresh. self-refresh operations are autonomously scheduled and performed by the cellularram device. bcr.bit <5:4> drive strength impedance typ. (ohm) 1) 1) the value is for reference only. not all samples tested . refer to ibis model for accurate i-v characteristics. use recommendation 00 b full 25~30 c l = 30pf or heavier 01 b (default) 1/2 50~60 c l = 15pf to 30pf ac test load for spec parameters 10 b 1/4 100~120 c l = 15pf or lighter don't care dq15-dq0 amax-a0 q0 adr clk wait adv q1 latency code2 read wc=1 (wait one clock earlier) q0 adr q1 read wc=0 (wait with data) 2 clocks 3 clocks latency code2 3 clocks 3 clocks (notes) wp=0 is shown
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 34 v1.5, 2005-5 2.6 device id register (didr) figure 18 device id register (didr) mapping device id register offers the way the user can check manufacturer?s id (5-bit), spec-compliance generation of cellularram (3-bit), density (3-b it), design version (4-bit), and page size (1-bit) information. this is read-only register, so that scr command has no effect to the content of didr. a18 input has to be applied high to select didr at fcr command timing when cre-controlled is used( figure 7 and figure 9 ). (read-only register) for bit 15 of page size, please ignore the readout in case that the information is not needed. didr device id register (cre, a18 = 11 b ) a18 bit15 bit14 bit13 bit12 bit11 bit10 bit9 b it8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 1 ps design version density generation manufacturer?s id page size design version densi ty spec_gen manufacturer?s id 0000 b : a 0001 b : b and so on 011 b : 128m 010 b : 1.5 00010 b : infineon m anufacturer?s id device id register (didr) : read-only dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 generation 00001 b cypress dq<4:0> vendor 001 b 1.0 dq<7:5> generation 010 b 1.5 011 b 2.0 consortium standard density design vesion 000 b : 1 6 m 001 b : 3 2 m 010 b : 6 4 m 011 b : 128m 100 b : 256m 0001 b : b 0010 b : c 0011 b : d (and so on) can be used for tech. node in fo rm a tio n , e rra ta , e tc. 0 b : 128-word 1 b : 256-word 0000 b : a page size 00010 b infineon 00011 b micron 00100 b renesas ps
data sheet 35 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2.7 considerati on on address skew it is understood that the skew among multiple address lines is unavoidable. however, the amount of it has to be well controlled for proper device operation. figure 19 timing diagram of address skew as depicted in figure 19 , 3 parameters have to be met to avoid any malfunction of the device. any valid address input when all active control signals - cs , ub , lb , and adv become low has to meet t rc. note: 1. in case of adv latching the address, this parameter is not applied. note: 2. in page read mode, 0ns is required for this parameter in case that inter-page address, a4 and higher change. table 12 timing parameters - address skew parameter symbol 9.6, 12.5 15 unit note min. max. min. max. read cycle time t rc 70?85?ns? address skew window t skew ?10?10ns? address set-up to the last active control signal low t ascl -10?-10?ns? address hold from the first active control signal high t chah 0?0?ns1, 2 don't care amax-a0 address cs t chah t ascl t rc t skew address *1 *2 *3 notes: 1. the parameter is referenced to the last falling edge among /cs, /ub, /lb, /adv to start memory access. 2. any address transition may be located in this range. 3. the parameter is referenced to the earliest rising edge among /cs, /ub, /lb, /we to end memory access.
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 36 v1.5, 2005-5 2.8 sram-type mode [disclaimer] amax for 64mbit cellularram is a21. a22 is for 128mbit density . wait signal is shown in the selected timing diagrams for the case of wp=0 (active low) though it is not default state. in sram-type mode, the cellu larram applies asynchronous sram protocol to perform read and write accesses. 2.8.1 asynchronous read after power-up the cellularram operates per default in asynchronous sram-type mode. the synchronous clock line, clk has to be held low, while address latch signal, adv can be held low for entire read and write operation in this mode or toggled to latc h valid address input (refer to ?asynchronous write with address latch (adv) control? on page 47 for detailed timing diagram and parameters as to toggling adv ). wait is asserted as bcr. bit 10 is programmed during cs low time, so that the controller should ignore wait during asynchronous mode operation . (not shown in all timing diagrams) reading from the device in asynchronous mode is accomplished by assertin g the chip select (cs ) and output enable (oe ) signals to low while forcing write enable (we ) to high. if the upper byte (ub ) control line is set active low then the upper word of the addressed data is driven on the output lines, dq15 to dq8. if the lower byte (lb ) control line is set active low then the lower word of the add ressed data is driven on the output lines, dq7 to dq0. the access time is determined by the triggering input - slowest one in low-going transition - in combination with access timing parameters among valid address ( t aa ), cs ( t co ), oe ( t oe ), ub or lb ( t ba ), or adv ( t aadv ). figure 20 asynchronous read - address controlled (cs = oe = v il , we = v ih , ub and/or lb = v il , cre = v il, adv = v il ) figure 21 asynchronous read (we = v ih , cre = v il ) not valid amax-a0 address data valid dq15-dq0 previous data t oh t aa t rc don't care amax-a0 address cs ub, lb oe data valid we dq15-dq0 t co t aa t ba t oe t blz t oh t ohz t bhz t rc t olz t lz adv t aadv t cph t hz t bph wait t wz t cwt (notes) wp=0 is shown
data sheet 37 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description figure 22 asynchronous control register read don't care amax-a0 cs we ub, lb dq15-dq0 t rc a19, a18 cre adv 00 b (rcr), 10 b (bcr), x1 b (didr) oe opcode t co t oe t crs t olz t ba t blz
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 38 v1.5, 2005-5 2.8.2 page mode if activated by rcr.bit7 page mode allows to toggle the four lower address bits (a3 to a0) to perform subsequent random read accesses (max. 16-words by a3 - a0) at much faster speed than 1 st read access. page mode operation supports only read access in cellularram. as soon as page mode is activated, cs low time restriction ( t csl ) applies. it is recommended to bring cs high and back low to access different page. therefore the usage of page mode is only recommended in systems which can respect this limitation. adv has to be held low for entire page operation. wait is always asserted as bcr. bit 10 is programmed as to cs low time, so that the controller should ignore wait during asynchronous mode operation. (not shown in the timing diagrams) figure 23 asynchronous page read mode (cre = v il, adv = v il ) don't care amax-a4 address cs ub, lb oe we dq15-dq0 t co t lz t blz t bhz t ohz t rc a3-a0 address t aa data adr adr adr adr t oh t csl t olz t hz adv t aadv t pc data data data data t paa
data sheet 39 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description note: the ac parameter is measured with default drive strength, 1/2. table 13 timing parameters - asynchronous read parameter symbol 9.6, 12.5 15 unit notes min. max. min. max. read cycle time t rc 70?85?ns? address access time t aa ?70?85ns? adv access time t aadv ?70?85ns? page address cycle time t pc 20?25?ns? page address access time t paa ?20?25ns? output hold from address change t oh 5?6?ns? chip select access time t co ?70?85ns? ub , lb access time t ba ?70?85ns? oe to valid output data t oe ?20?25ns? chip select pulse width low time t csl ?4?4 s? chip select to output active t lz 6?6?ns? chip select disable to high-z output t hz ?8?8ns? ub , lb enable to output active t blz 6?6?ns? ub , lb disable to high-z output t bhz ?8?8ns? output enable to output active t olz 3?3?ns? output disable to high-z output t ohz ?8?8ns? cs high time when toggling t cph 10?15?ns? ub , lb high time when toggling t bph 10?15?ns? cre setup time to chip select low t crs 0?0?ns? cs low to wait valid t cwt 17.517.5ns? cs high to wait high-z t wz 0808ns?
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 40 v1.5, 2005-5 2.8.3 asynchronous write [disclaimer] amax for 64mbit cellularram is a21. a22 is for 128mbit density . wait signal is shown in the selected timing diagrams for the case of wp=0 (active low) though it is not default state. writing to the device in asynchronous sram mode is accomplished by assert ing the chip select (cs ) and write enable (we ) signals to low. adv can be used to latch the address (refer to ?asynchronous write with address latch (adv) control? on page 47 for detailed timing diagram and parameters as to toggling adv ) or simply held low for entire write operation. if the upper byte (ub ) control line is set active low then the upper word (dq15 to dq8) of the data bus is written to the specified memory location. if the lower byte (lb ) control line is set active low then the lower word (dq7 to dq0) of the data bus is written to the specified memory location. write operation takes place when either one or both ub and lb is asserted low. the data is latched by the rising edge of either cs , we , or ub /lb whichever signal comes first. wait is always asserted as bcr. bit 10 is programmed as to cs low time, so that the controller should ignore wait during asynchronous mode operation . (not shown in all timing diagrams) figure 24 asynchronous write - we controlled (oe = v ih or v il , cre = v il ) figure 25 asynchronous write - cs controlled (oe = v ih or v il , cre = v il ) don't care amax-a0 address cs we ub, lb dq15-dq0 t cw t wr t wc t wp t aw t bw data valid wait t ds t dh t as t whz t ow adv t wph t wz t cwt (notes) wp=0 is shown don't care amax-a0 address cs we ub, lb wait t cw t wc t as t wp t ds t dh t bw data in valid dq15-dq0 high-z t lz, t blz t whz adv t cph t wr t aw t wz t cwt high-z (notes) wp=0 is shown
data sheet 41 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description figure 26 asynchronous write - ub , lb controlled (oe = v ih or v il , cre = v il ) the programming of control register in sram-type mode is performed in the similar manner as asynchronous write except cre being held high during the operation. note that cre has to meet set-up ( t cres ) and hold time ( t creh ) of valid state (= high) in reference to we falling and rising edge, respectively. adv may be kept low for entire operation. cs should toggle at the end of the operation to get ready for following access. figure 27 asynchronous write to control register (oe = v ih or v il ) don't care amax-a0 address cs we ub, lb t cw t wc t as t wp t bw data in valid t ds t dh adv t bph t wr t aw dq15-dq0 wait t wz t cwt t lz, t blz t whz high-z low (notes) wp=0 is shown don't care amax-a0 op code cs we ub, lb wait t cw t wr t wc t wp t aw dq15-dq0 t as t crh t crs high-z a19 cre adv 0(rcr), 1(bcr) high-z t wph t aw t cwt t wz (notes) wp=0 is shown
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 42 v1.5, 2005-5 note: the ac parameter is measured with default drive strength, 1/2. table 14 timing parameters - asynchronous write parameter symbol 9.6, 12.5 15 unit notes min. max. min. max. write cycle time t wc 70?85?ns? address (incl. cre) set-up time t as 0?0?ns? address valid to end of write t aw 70?85?ns? write recovery time t wr 0?0?ns? chip select pulse width low time t csl ?4?4 s? chip select to end of write t cw 70?85?ns? adv setup to end of write t vs 70?85?ns? byte control valid to end of write t bw 70?85?ns? write pulse width t wp 45?55?ns? write pulse pause t wph 10?15?ns? cs high time when toggling t cph 10?15?ns? ub , lb high time when toggling t bph 10?15?ns? write to output disable t whz ?8?10ns? end of write to output enable (oe = low) t ow 5?5?ns? write data setup time t ds 20?25?ns? write data hold time t dh 0?0?ns? cre setup time to chip select low t crs 0?0?ns? cre hold time from we high t crh 0?0?ns? cs low to wait valid t cwt 17.517.5ns? cs high to wait high-z t wz 0808ns?
data sheet 43 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2.9 nor-flash-type mode [disclaimer] amax for 64mbit cellularram is a21. a22 is for 128mbit density. in nor-flash mode the cellularram applies the nor-flash protocol to perform read and write accesses to the memory. read accesses can be executed in synchronous burst mode, while write accesses are executed in asynchronous mode using adv as address latch strobe signal. 2.9.1 synchronous read mode [disclaimer] wait signal of all synchronous timings below is shown in the case of wc=0 (at delay) and wp=0 (active low) though it is not default state. detailed description about burst operation including latenc y mode/code, bl, wrap, wait function, etc. is available in ?bus control register? on page 25 . proper setting of bcr has to be preceded to any burst operation. in synchronous read mode all operations are referred to the rising clock signal edge. refresh cycles or row boundary crossings are indicated by the wait output signal which stalls the processor for this period. row boundary crossing is not permitted in case of bcr.bit14 = 1 (fixed latency mode). figure 28 synchronous read burst (cre = v il ) don't care cs oe ub, lb we dq15-dq0 t hd t od amax-a0 q0 adr clk wait adv t sp t css q2 q3 q4 t clk t ckh t ckl t koh t wk q1 in case of lat=2, 3 within variable latency range, additional wait cycles to the programmed latency might be inserted if the burst read access collides with an ongoing refresh cycle. latency code2 t sp t vp t aba t cbph t ol t cwt t wz t aclk t sp t hd t hd t aoe [row boundary crossing] wait is asserted back to indicate the situation. new command can be issued in case wait monitoring is not available. t hd t sp (notes) wp=0, wc=0 is shown row boundary crossing is not supported
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 44 v1.5, 2005-5 2.9.2 burst suspend while in synchronous burst operation, the bus interface may need to be assigned to other memory transaction sharing the same bus. burst suspend mode is used to fulfill this op eration. keeping cs low (wait stays asserted indicating valid data output on dq pins, though they are tri-stated), burst suspend can be initiated with halted clk. clk can stay at either high or low state. as specified, duration of keeping cs low can not exceed t csl maximum, which is 4 s, so that internal refresh operation is able to run properly. in this event of exceeding t csl maximum, termination of burst by bringing cs to high is strongly recommended instead of using burst suspend mode, then reissuing of the discontinued burst command is required. figure 29 burst suspend (cre = v il ) don't care cs oe ub, lb we dq15-dq0 t aoe t hd t od amax-a0 q0 adr clk wait adv t sp t css q1 q2 q3 t clk t ckh t ckl t koh t wk q1 latency code2 t sp t vp t aba t cbph t ol t cwt t wz t aclk t sp t hd t hd t od t ol burst suspend /cs low time in burst suspend should not exceed 8us for internal refresh operation. t csl *1 *1: in case /oe being held low, q1 is maintained on dq t hd t sp (notes) wp=0, wc=0 is shown
data sheet 45 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2.9.3 synchronous control register read the content of rcr, bcr, or ridr is readable via dq pins by cre-controlled fcr command. a19 and a18 selects the register to be accessed. it is identical to single-bit read access in burst operation, but the latency is always the same as being programmed in bcr, though it is in variable latency mode. refresh is not performed during burst_init phase of this command, so that cs should not exceed t csl,max limit. figure 30 synchronous control register read in the timing diagram, the timing between cre and we has to be carefully controlled since the overlap of cre high and we low may accidentally program the control register. asyn chronous command of op eration is still valid when the synchronous command is prepared. plea se avoid the time when both cre high and we low is met. in the same manner, the time when both cs and we low has to be avoided at the set up of synchronous read command for normal burst or control register access to avoid accidental asynchronous write operation. hi-z don't care cs oe ub, lb we dq15-dq0 amax-a0 clk wait adv t cl k cre a19, a18 t css t cwt t hd t sp 00 b (rcr), 10 b (bcr), x1 b (didr) t hd t sp t sp t hd t sp t ao e t hd t vp opcode ub, lb (notes) wp=0, wc=0 is shown
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 46 v1.5, 2005-5 table 15 timing parameters - synchronous read burst parameter symbol 9.6 12.5 15 unit notes min. max. min. max. min. max. clock period frequency (variable latency) lat = 3 f clk3v ?104?80?66mhz? lat = 2 f clk2v ?66?66?40mhz? clock period (variable latency) lat = 3 t clk3v 9.6 ? 12.5 ? 15 ? ns ? lat = 2 t clk2v 15?15?25?ns? clock period frequency (fixed latency) lat = 6 f clk6f ?104?80?66mhz? lat = 5 f clk5f ?75?75?52mhz? lat = 4 f clk4f ?66?66?40mhz? lat = 3 f clk3f ?52?52?33mhz? lat = 2 f clk2f ?33?33?20mhz? clock period (fixed latency) lat = 6 t clk6f 9.6 ? 12.5 ? 15 ? ns ? lat = 5 t clk5f 13.3 ? 13.3 ? 19.2 ? ns ? lat = 4 t clk4f 15?15?25?ns? lat = 3 t clk3f 19.2 ? 19.2 ? 30 ? ns ? lat = 2 t clk2f 30?30?50?ns? clock high time t ckh 3?4?5?ns? clock low time t ckl 3?4?5?ns? clock rise/fall time t t ?1.6?1.8? 2ns? input setup time to clk (except cs ) t sp 3?4?5?ns? input hold time from clk t hd 2?2?2?ns? adv pulse width low t vp 5?6?7?ns? burst read 1 st access delay from clk t aba ?36?39?56ns 1) cs low setup to clk t css 3?4?5?ns chip select pulse width low time t csl ?4?4?4 s? cs pulse width high t cbph 5?6?8?ns? oe or lb /ub low to output low-z t ol 3?3?3?ns? cs , oe , or lb /ub high to output high-z t od 080808ns? oe low to output delay t aoe ?20?20?25ns? cs low to wait valid t cwt 17.517.517.5ns? cs high to wait high-z t wz 080808ns? clk to wait valid t wk ?7?9?11ns? clk to output delay t aclk ?7?9?11ns? output hold from clk t koh 2?2?2?ns? 1) this is based on the use of variable latency. in case of re fresh collision to the first acce ss, more wait cycles will be adde d. note: the ac parameter is measured with default driv e strength, 1/2.
data sheet 47 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description 2.9.4 asynchronous write with address latch (adv ) control in asynchronous write mode, the synchronous clock is switched off and clk has to be held low. the access protocol is shown with adv -latching scheme and it can be applied to write operation in sram-type mode. wait is always asserted as bcr. bit 10 is programmed as to cs low time, so that the controller should ignore wait during asynchronous mode operation. figure 31 asynchronous write with address latch (adv ) control (followed by single-burst read) figure 32 asynchronous write with address latch (adv ) control asynchronous write operation may be executed in a conjuction with a read burst operation. bringing cs high is recommended to stop a read burst if it is on-going. don't care amax-a0 address cs we ub, lb data input oe dq15-dq0 t cw t wp t ds t dh t vp adv t avs t avh t wph t cka t wc t vs t bw t as t wr t aw q0 adr t css t wk latency code2 t vp t aba t ol t cwt t aclk t sp t hd t cph wait t od t cbph t wz t aoe t koh t hd t sp t sp t hd t hd t cvp t wz t cwt (notes) wp=0, wc=0 is shown don't care amax-a0 cs we ub, lb oe dq15-dq0 adv address data input t cw t wp t ds t dh t vp t avs t avh t wph t wc t vs t bw t as t wr t aw clk t cbph qa qb t hz t cvp wait t wz t cwt (notes) wp=0, wc=0 is shown
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 48 v1.5, 2005-5 however it is allowed to le t asynchronous write operation follow a read burst while cs is held low and clk is stopped at low. by adv being pulled low with valid write timing as in figure 32 , asynchronous write operation can be done. please note that the on-going burst is terminated before write operation is initiated when adv goes low. the programming of control register in nor-flash-type mode is performed in the similar manner as asynchronous write with adv control except cre being held high during the code input operation. note that cre has to meet set-up ( t crs ) and hold time ( t crh ) of valid state (= high) in reference to adv rising edge. adv may be kept low for entire operation or go high to latch valid control register information at its rising edge. figure 33 asynchronous write to control register in nor-flash mode don't care amax-a0 opcode cs we ub, lb oe dq15-dq0 t cw t wp t vp adv address t avs t avh t wph t cka t wc t vs cre a19 t crs t crh 0(rcr), 1(bcr) t aw t cvp
data sheet 49 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description note: 1. t wr is valid only when adv latch of address does not take place until the end of write. note: the ac parameter is measured with default driv e strength, 1/2. table 16 timing parameters - asynchronous write with adv control parameter symbol 9.6, 12.5 15 unit notes min. max. min. max. we high to clk valid t cka 25?35?ns? write cycle time t wc 70?85?ns? address setup time to write start t as 0?0?ns? address setup to adv high t avs 5?5?ns? address hold from adv high t avh 2?2?ns? address to end of write t aw 70?85?ns? adv pulse width low t vp 5?7?ns? adv low hold time for cs low t cvp 7?7?ns? adv setup to end of write t vs 70?85?ns? cs to end of write t cw 70?85?ns? ub /lb to end of write t bw 70?85?ns? write pulse width low t wp 45?55?ns? write pulse width high t wph 10?15?ns? cs high time (synch_read) t cbph 5?8?ns? cs high time (asynch_write, mixed) t cph 10?15?ns? write recovery time t wr 0?0?ns1 data setup to we high t ds 20?25?ns? data hold from we high t dh 0?0?ns? cre setup to adv high t crs 5?5?ns? cre hold from adv high t crh 2?2?ns? wait valid from cs low t cwt 17.517.5ns? cs high to wait high-z t wz 0808ns? chip select pulse width low time t csl ?4?4 s?
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 50 v1.5, 2005-5 2.10 synchronous mode [disclaimer] amax for 64mbit cellularram is a21. a22 is for 128mbit density. wait signal of all synchronous timings below is shown in the case of wc=0 (at delay) and wp=0 (active low) though it is not default state. detailed description about burst operation including latenc y mode/code, bl, wrap, wait function, etc. is available in ?bus control register? on page 25 . proper setting of bcr has to be preceded to any burst operation. in synchronous mode, read and write operations are synch ronized to the clock. refresh cycles or row boundary crossings are indicated to the host system by asserting the wait signal which in turn stalls the processor. row boundary crossing is not permitted in fixed latency mode setting (bcr.bit14 = 1). wait polarity, wait timing, synchronicity to the falling/rising clock edge, the burst le ngth and further options are user configurable and can be programmed via the bus configuration register (bcr). 2.10.1 synchronous read mode including burst suspend refer to section 2.9.1 and section 2.9.2 . all the timing and parameters are same as described in read operation for nor-flash-type mode. 2.10.2 synchronous write mode in synchronous write mode, ub and lb are used as byte control of data input mask. at the rising edge of clk, their state is sampled and determined whether the coupled byte (dq15-8 for ub and dq7-0 for lb ) is updated by input data. proper set-up time and hold time to clk should be met. as discussed in section 2.4.1.3 , synchronous burst write always works with fixed latency concept, therefore, t csl maximum, which is 4 s, has to be observed. figure 34 synchronous write burst (cre = v il ) hi-z don't care cs oe ub, lb we dq15-dq0 t hd amax-a0 adr clk wait adv t sp t css t clk t ckh t ckl t hd t hd unlike read burst, write burst always produce the same latency as programmed in bcr. d0 d1 d2 d3 d4 t wz t cbph t wk t cwt latency code2 t sp t hd (mask) t vp t hd t sp t sp t sp t wc t csl row boundary crossing: always programmed latency(lc) is inserted (lc+1 clock cycles with invalid data) t hd t sp t kadv row boundary crossing is not supported (notes) wp=0, wc=0 is shown
data sheet 51 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description t kadv has to be observed to ensure the completion of write operation and recovery. this parameter defines the time required from the last data-in to new burst start. t kadv applies to only when the new burst_init command is either write burst in variable latency mode or read burst in fixed latency mode so that the refresh operation is properly performed in case. this parameter does not apply to the burst interrupt case when cs stays low. though maximum of t css is not specified when a write burst command is asserted, it is strongly recommended not to exceed it 20ns. however, in case of longer, extended t css timing being in use, the special care has to be taken to the address line update as to we low-going time. figure 35 illustrates the case for de tails. address set-up time, t as is still valid in this range since th e command is identified as asynchron ous command until the valid clock edge comes in to start burst operation. the update of address line after we low-going is not permitted. figure 35 synchronous write command with extended t css burst suspend mode is also available during a write burst. please refer to section 2.9.2 for details. don't care cs we amax-a0 addr clk adv t css > 20ns t hd t sp t as
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 52 v1.5, 2005-5 figure 36 synchronous write to control register hi-z don't care cs oe ub, lb we dq15-dq0 amax-a0 opcode clk wait adv t clk t ckh t ckl t wz cre a19 t hd t sp t css t cwt t hd t sp 0(rcr), 1(bcr) t hd t sp t sp t hd t sp t hd t vp (notes) wp=0, wc=0 is shown
data sheet 53 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description figure 37 synchronous write burst followed by synchronous read burst figure 38 synchronous read burst followed by synchronous write burst hi-z don't care cs oe ub, lb we dq15-dq0 amax-a0 clk wait adv t clk t ckh t ckl in case the burst read access collides with an ongoing refresh cycle additional wait cycles might be inserted d0 d1 d2 d3 t wz t cbph t wk t cwt latency code2 /cs high stops write burst adr t aoe t hd t od q0 adr t sp t css q2 q3 t koh t wk q1 latency code2 t aba t cbph t ol t cwt t wz t aclk t hd t sp t hd t hd t hd t sp t hd t sp t css t hd t sp t vp always the same latency for write burst t wc t rc t hd t sp t vp t hd t sp t sp t sp (notes) wp=0, wc=0 is shown (hi-z) don't care cs oe ub, lb we dq15-dq0 amax-a0 clk wait adv t css in case the burst access collides with an ongoing refresh cycle additional wait cycles might be inserted d0 d1 d2 d3 t wk t cwt latency code2 t wz t od q0 adr t css q2 q3 t clk t ckh t ckl t koh t wk q1 latency code2 t aba t cbph t ol t cwt t wz t aclk t sp t hd t hd t aoe t sp t hd t vp adr t hd t sp t sp t hd t hd t hd t sp always the same latency for burst write t rc t wc t sp t hd t vp t hd t sp t sp t sp (notes) wp=0, wc=0 is shown
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) functional description data sheet 54 v1.5, 2005-5 2.11 general ac input/out put reference waveform the input timings refer to a midlevel of v ddq /2 while as output timings refer to midlevel v ddq /2. the rising and falling edges are 10 - 90% and < 2 ns. table 17 timing parameters - synchronous read/write burst parameter symbol 9.6 12.5 15 unit notes min. max. min. max. min. max. clock period frequency (variable latency) lat = 3 f clk3v ?104?80?66mhz? lat = 2 f clk2v ?66?66?40mhz? clock period (variable latency) lat = 3 t clk3v 9.6 ? 12.5 ? 15 ? ns ? lat = 2 t clk2v 15?15?25?ns? clock period frequency (fixed latency) lat = 6 f clk6f ?104?80?66mhz? lat = 5 f clk5f ?75?75?52mhz? lat = 4 f clk4f ?66?66?40mhz? lat = 3 f clk3f ?52?52?33mhz? lat = 2 f clk2f ?33?33?20mhz? clock period (fixed latency) lat = 6 t clk6f 9.6 ? 12.5 ? 15 ? ns ? lat = 5 t clk5f 13.3 ? 13.3 ? 19.2 ? ns ? lat = 4 t clk4f 15?15?25?ns? lat = 3 t clk3f 19.2 ? 19.2 ? 30 ? ns ? lat = 2 t clk2f 30?30?50?ns? clock high time t ckh 3?4?5?ns? clock low time t ckl 3?4?5?ns? clock rise/fall time t t ?1.6?1.8? 2ns? input setup time to clk (except cs ) t sp 3?4?5?ns? input hold time from clk t hd 2?2?2?ns? adv pulse width low t vp 5?6?7?ns? burst read 1 st access delay from clk t aba ?36?39?56ns 1) cs low setup to clk t css 3?4?5?ns 2) chip select pulse width low time t csl ?4?4?4 s? cs pulse width high t cbph 5?6?8?ns? oe or lb /ub low to output low-z t ol 3?3?3?ns? cs , oe , or lb /ub high to output high-z t od 080808ns? oe low to output delay t aoe ?20?20?25ns? cs low to wait valid t cwt 17.517.517.5ns? cs high to wait high-z t wz 080808ns? clk to wait valid t wk ?7?9?11ns? clk to output delay t aclk ?7?9?11ns? output hold from clk t koh 2?2?2?ns? last data-in to new adv low t kadv 15?15?15?ns 3) 1) this is based on the use of variable latency. in case of re fresh collision to the first acce ss, more wait cycles will be adde d. 2) maximum value is recommended not to exceed 20ns. in case of longer than 20ns, no address change is permitted after we goes low to set up a write burst command. 3) this applies to only when the next burst_init command is eith er write burst in variable latency mode or read burst in fixed latency mode. burst write interrupted by any burst (while cs is low) does not ask for t kadv. note: the ac parameter is measured with default drive strength, 1/2.
data sheet 55 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) electrical characteristics 3 electrical characteristics 3.1 absolute maximum ratings attention: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 3.2 recommended power & dc operation ratings all values are recommended operati ng conditions unless otherwise noted. table 18 absolute maximum ratings parameter symbol limit values unit notes min. max. operating temperature range t c -30 +85 c ? storage temperature range t stg -55 +150 c ? soldering peak temperature (10 s) t sold ?260c? voltage of v dd supply relative to v ss v dd -0.3 +2.5 v ? voltage of v ddq supply relative to v ss v ddq -0.3 +2.5 v ? voltage of any input relative to v ss v in -0.3 +2.8 v ? power dissipation p d ?180mw? short circuit output current i out -50 +50 ma ? table 19 recommended dc operating conditions parameter symbol limit values unit notes min. typ. max. power supply voltage, core v dd 1.70 1.8 1.95 v ? power supply voltage, 1.8 v i/os v ddq 1.70 1.8 1.95 v ? input high voltage v ih v ddq ? 0.4 ? v ddq + 0.2 v 1) 1) input signals may overshoot no higher than v ddq +1.0v. the area above v ddq should not exceed 2v-ns. input low voltage v il -0.2 ? 0.4 v 2) 2) input signals may undershoot no lower than -1.0v. the area below v ssq should not exceed 2v-ns. table 20 dc characteristics parameter symbol limit values unit notes min. typ. max. output high voltage ( i oh = -0.2 ma) v oh v ddq 0.8 ? ? v ? output low voltage ( i ol = 0.2 ma) v ol ?? v ddq 0.2 v ? input leakage current i li ??1 a? output leakage current i lo ??1 a?
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) electrical characteristics data sheet 56 v1.5, 2005-5 3.3 output test conditions figure 39 dc / ac output test circuit please refer to section section 2.11 . 3.4 pin capacitances table 21 operating characteristics parameter symbol 9.6 12.5 15 unit test condition notes min. max. min. max. min. max. operating current async read/write random @ t rcmin async read/write random @ t rc =1 s async page read burst initial access sync burst (continuous) read sync burst (continuous) write i dd1 i dd1l i dd1p i dd2 i dd3r i dd3w ? ? ? ? ? ? 25 5 18 40 30 35 ? ? ? ? ? ? 25 5 18 35 25 30 ? ? ? ? ? ? 20 5 15 30 20 25 ma v in = v dd or v ss , chip enabled, i out = 0 50% of data switching 1) 2) stand-by current i sb ?250?250?250 a v in = v dd or v ss ,chip deselected, (full array) ? parameter symbol all speed grades unit test condition notes typ. max. deep power down current i dpd 10 25 a v in = v dd or v ss ? 1) the specification assu mes the output disabled. 2) it is measured as page address <3:0> is applied sequentially (0000 b -0001 b -0010 b -...-1111 b -0000 b -...). table 22 pin capacitances pin limit values unit condition min. max. a22 - a0, cs , oe , we , ub , lb , cre, adv 2.0 6.0 pf t a = +25 c freq. = 1 mhz v pin = 0 v (sampled, not 100% tested) clk 2.0 6.0 pf dq15 - dq0 2.5 6.0 pf wait 2.5 6.0 pf 30pf test point vddq/2 dut 50 ohm ac test load 30pf test point vddq dut 5.4k ohm dc test load 5.4k ohm
data sheet 57 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) package outlines 4 package outlines figure 40 pg-vfbga-54 (plastic very thin fine pitch ba ll grid array package - green package) 6.00 0.10 + _ 8.00 0.10 + _ ball a1 indicator top view 6.00 typ 3.75 typ 0.75 typ ball a1 0.75 typ balls view 54x 0.35 (pre-reflow diameter is 0.35) 1.00 max 0.23 typ seating plane c note: 1. all dimensions in mm 2. primary datum c and seating plane are defined by high points of solder balls. s md = surface mounted device y ou can find all of our packages, sorts of packing and others in our i nfineon internet page ?products?: http://www.infineon.com/products . dimensions in m m
hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) appendix : s/w register entry mode (?4-cycle method?) data sheet 58 v1.5, 2005-5 5 appendix : s/w register en try mode (?4-cycle method?) other than cre-controlled scr and fcr operation, cellularram supports software (s/w) method as an alternative to access the control registers. since s/w regi ster entry mode consists of 4 consecutive access cycles to top memory location (all addresses are ?1?), it is often re ferred as ?4-cycle method?. 4-cycles starts from 2 back- to-back read cycles (initializing co mmand identification) followed by on e write cycle (command identification completed and which control register is accessed is known), then final write cycle for configuring the selected control register by the given input or read cycle to check the content of the register through dq pins. it does function the configuration of control register bits like the way with dedicated pin, cre method, but there are a few differences from cre-controlled method as follow; register read mode (checking content) is supported with s/w register entry as well as register write (program). the mode bits for control register are supplied through dq <15:0> instead of address pins in cre-controlled. though each register has 23-bits (a<22:0>) for 128m cellularram, only low 16-b it registers becomes valid during s/w method. only asynchronous read a nd write is allowed for consecutive 4 acce ss cycles to top address. no synchronous timing is supported. if this entry mode is used in synchronous mode, then clock should stop running and stay at low level. instead of a19 or a18 state, the selection of the control register, bcr or rcr, or didr is done with the state of dq<15:0> given at 3rd cycle. (?00 h ? for rcr, ?01 h ? for bcr, ?02 h ? for didr) the method is realized by the device exactly when 2 consecutive read cycles to top memory location is followed by write cycle to the same location, so that any exceptional cycle combinat ion - not only access mode, but also the number of cycles - will fail in in voking the register entry mode properly. figure 41 s/w register entry timing (address input = 7fffff h ) as depicted in figure 41 , 4-cycle operation requires the following timing requirement which are not applied to normal asynchronous read or write cycles. cs has to toggle in every cycle to distinguish 4 consecutive cycles. address input of top memory location has to be maintained until the completion of each cycle by simply holding all address signals high or latching them by adv until cs goes high. don't care amax-a0 all ?1?s cs ub, lb oe we dq15-dq0 t rc adv all ?1?s all ?1?s 0000h(rcr), 0001h( bcr), 0002h(didr) all ?1?s ` register bits read to top memory location (1 st ) read to top memory location (2nd) write to top memory location write or read to top memory location (cycle type) (function) wait for next write to confirm s/w register entry select rcr, bcr, or didr (write) configure selected register by dq inputs (read) output selected register contents through dq t wc
data sheet 59 v1.5, 2005-5 hye18p128160af-9.6/12.5/15 128m synchronous burs t cellularram tm (1.5g) appendix : s/w register entry mode (?4-cycle method?) figure 42 rcr mapping in s/w register entry figure 43 bcr mapping in s/w register entry figure 44 didr mapping in s/w register read pasr refreshed memory area a2 a1 a0 partial array self refresh 001 010 dq 0 entire memory array (def.) 000 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 dq 8 dq 15 (tcsr)* pm 0 0 temperature-compensated self-refresh (no effect) dq bus control register deep power down mode 011 lower 1/2 of memory array lower 1/4 of memory array lower 1/8 of memory array 101 110 111 upper 1/2 of memory array upper 1/4 of memory array upper 1/8 of memory array zero 100 page mode page mode bit disabled (def.) enabled 0 1 a7 dpd 0 dpd disabled (def.) enabled 0 1 a4 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 8 dq 9 dq 10 dq 11 dq 12 dq 13 dq 14 dq 15 dq bus dq 9 burst length burst length bw wp wc imp om drive strength output impedance full drive 1/4 drive 0 0 a4 latency code latency latency code reserved code3 (def) 011 polarity wait polarity active low active high (def) 0 1 a10 opmode operation mode sync mode 0 1 a15 control register timing wait configuration at delay one data cycle in advance (def) 0 1 a8 async./ page mode (def) a11 a12 a13 code2 010 0 0 1 a5 1/2 drive (def) 1 0 reserved 1 1 101 code4 100 code5 reserved code6 110 a2 a1 a0 all others reserved continuous (def) 111 8 010 4 001 16 011 wrap mode burst wrap wrap no wrap (def) 0 1 a3 length 0 lm latency mode all others 1 a14 1 1 0 0 all others 0 1 variable fixed 0 32 100 1 0 1 1 code3 1 0 1 0 code2 (note) setting of bit.6 has no effect manufacturer?s id device id register (didr) : read-only dq15 dq14 dq13 dq12 dq11 dq10 dq9 dq8 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 by 0002 h generation 00010 b infineon dq<4:0> vendor 001 b 1.0 dq<7:5> generation 010 b 1.5 011 b 2.0 density design vesion 000 b : 16m 001 b : 32m 010 b : 64m 011 b : 128m 100 b : 256m 0001 b : b 0010 b : c 0011 b : d (and so on) 0000 b : a 0 b : 128-word 1 b : 256-word ps
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